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dual-channel isolators with integrated dc/dc converter preliminary technical data adum5200/5201/5202 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features iso power? integrated isolated dc/dc converter regulated 3v or 5v output 500mw output power dual dc-to-25 mbps (nrz) signal isolation channels schmitt trigger inputs soic 16-lead package with > 8mm creepage high temperature operation: 105c high common-mode transient immunity: > 25 kv/s safety and regulatory approvals (pending) ul recognition 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications rs-232/rs-422/rs-485 transceiver industrial field bus isolation power supply start up and gate drive isolated sensor interface industrial plc general description the adum520x 1 are dual-channel digital isolators with isopower, an integrated, isolat ed dc/dc converter. based on analog devices i coupler? technology, the dc/dc converter provides up to 500 mw of regulated, isolated power at either 5.0v from a 5.0v input supply or 3.3v from a 3.3v or 5.0v supply. this eliminates the need for a separate isolated dc/dc converter in low-power isolated designs. analog devices chip- scale transformer i coupler technology is used both for the isolation of the logic signals as well as for the dc/dc converter. the result is a small form-factor total-isolation solution. adum520x units may be used in combination with adum540x and adum5000 with iso power to achieve higher output power levels and greater channel counts. the adum520x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see ordering guide). functional block diagrams figure 1adum520x functional diagrams 1 protected by u.s. patents 5,952,849, 6,873,065. and 7075 329 b2, other patents pending.
preliminary technical data adum5200/5201/5202 rev. pra | page 2 of 23 table of contents applications....................................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics C 5v primary input supply / 5v secondary isolated supply .......................................................... 3 electrical characteristics C 3.3v primary input supply / 3.3v secondary isolated supply .......................................................... 5 electrical characteristics C 5v primary input supply / 3.3v secondary isolated supply .......................................................... 7 package characteristics ............................................................... 9 insulation and safety-related specifications............................ 9 din v vde v 0884-10 (vde v 0884-10) insulation characteristics ............................................................................ 10 recommended operating conditions .................................... 10 absolute maximum ratings.......................................................... 11 esd caution................................................................................ 11 pin configuration and function descriptions........................... 12 typical performance characteristics ....................................... 15 application information................................................................ 17 theory of operation ................................................................... 18 pc board layout ........................................................................ 18 thermal analysis ....................................................................... 18 propagation delay-related parameters................................... 19 dc correctness and magnetic field immunity........................... 19 power consumption .................................................................. 20 insulation lifetime ..................................................................... 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history
preliminary technical data adum5200/5201/5202 rev. pra | page 3 of 23 specifications electrical characteristics C 5v primary input supply / 5v secondary isolated supply 1 4.5 v v dd1 5.5 v, v sel =v iso ; all voltages are relative to their respective ground. all min/max specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd = 5.0 v, v iso = 5.0 v, v sel = v iso . table 1. parameter symbol min typ max unit test conditions setpoint v iso 4.7 5.0 5.4 v i iso =0ma line regulation v iso(line) 1 mv/v i iso =50ma, v dd1 =4.5v to 5.5v load regulation v iso(load) 1 5 % i iso = 10ma to 90ma output ripple v iso(rip) 75 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 100ma output noise v iso(n) 200 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 100ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz dc to 2 mbps data rate 2 maximum output supply current 3 i iso(max) 100 ma f 1 mhz, v iso =5v efficiency at max. output supply current 4 34 % i iso = i iso(2,max) , f 1 mhz i dd1 supply current, no v iso load 5 i dd1(q) 19 30 ma i iso = 0ma, f 1 mhz 25 mbps data rate (crwz grade only) i dd1 supply current, no v iso load 6 adum5200 i dd1(d) 34 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5201 i dd1(d) 38 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5202 i dd1(d) 41 ma i iso = 0ma, c l =15pf, f = 12.5 mhz available v iso supply current 7 adum5200 i iso(load) 94 ma c l =15pf, f = 12.5 mhz adum5201 i iso(load) 92 ma c l =15pf, f = 12.5 mhz adum5202 i iso(load) 90 ma c l =15pf, f = 12.5 mhz i dd1 supply current, full v iso load 8 i dd1(max) 290 ma c l =0pf, f = 0 mhz, v dd = 5v i iso =100ma i/o input currents i ia , i ib ?10 +0.01 +10 a logic high input threshold v ih 0.7 v iso v logic low input threshold v il 0.3 v iso v logic high output voltages v oah , v obh v dd1 ? 0.3, v iso ? 0.3 5.0 v i ox = ?20 a, v ix = v ixh v oah , v obh v dd1 ? 0.3, v iso ? 0.3 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.1 v i ox = 20 a, v ix = v ixl v oal , v obl 0.0 0.4 v i ox = 4 ma, v ix = v ixl ac specifications adum520xarwz minimum pulse width 9 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 10 1 mbps c l = 15 pf, cmos signal levels propagation delay 11 t phl , t plh 55 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 11 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 12 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 13 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum520xcrwz minimum pulse width 9 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 14 25 mbps c l = 15 pf, cmos signal levels propagation delay 15 t phl , t plh 45 60 ns c l = 15 pf, cmos signal levels
adum5200/5201/5202 preliminary technical data rev. pra| page 4 of 23 parameter symbol min typ max unit test conditions pulse-width distortion, |t plh ? t phl | 11 pwd 6 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/ c c l = 15 pf, cmos signal levels propagation delay skew 16 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 17 t pskcd 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 17 t pskcd 15 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output |cm h | 25 35 kv/s v ix = v dd or v iso , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output |cm l | 25 35 kv/s v ix = 0 v, v = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 all voltages are relative to their respective ground. 2 the contributions of supply current values for all four channels are combined at identical data rates. 3 v iso supply current available for external use when all data rates are below 2mbps. at data rates above 2mbps data i/o channels wi ll draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and be included in the v iso power budget. 4 the power demands of the quiescent operation of the data channels cannot be separated from the power supply section. efficien cy includes the quiescent power consumed by the i/o channels as part of its internal power consumption. 5 i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operat ing below 2mbps, requiring no additional dynamic supply curr ent. it reflects the minimu m current operating condition. 6 i dd1(d) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dynamic load conditions. resistive lo ads on the outputs should be treate d separately from the dynamic load. 7 this current is available for driving external loads at the v iso pin. all channels are simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dyn amic load conditions. refer to power consumption section for calculation of available current at l ess than maximum data rate. 8 i dd1(max) is the input current under full dynamic and v iso load conditions. 9 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 12 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 13 channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operat ed with identical loads.
preliminary technical data adum5200/5201/5202 rev. pra | page 5 of 23 electrical characteristics C 3.3v primary input supply / 3.3v secondary isolated supply 1 3.0 v v dd1 3.6 v, v sel =gnd iso ; all voltages are relative to their respective ground. all min/max specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd = 3.3 v, v iso = 3.3 v, v sel = gnd iso . table 2. parameter symbol min typ max unit test conditions setpoint v iso 3.13 3.3 3.37 v i iso =0ma line regulation v iso(line) 1 mv/v i iso =37.5 ma, v dd1 =3.0v to 3.6v load regulation v iso(load) 1 5 % i iso = 6ma to 54ma output ripple v iso(rip) 50 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 90ma output noise v iso(n) 130 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 90ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz dc to 2 mbps data rate 2 maximum output supply current 3 i iso(max) 60 ma f 1 mhz, v iso =3.15v efficiency at max. output supply current 4 36 % i iso = i iso(2,max) , f 1 mhz i dd1 supply current, no v iso load 5 i dd1(q) 10 20 ma i iso = 0ma, f 1 mhz 25 mbps data rate (crwz grade only) i dd1 supply current, no v iso load 6 adum5200 i dd1(d) 23 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5201 i dd1(d) 25 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5202 i dd1(d) 28 ma i iso = 0ma, c l =15pf, f = 12.5 mhz available v iso supply current 7 adum5200 i iso(load) 106 ma c l =15pf, f = 12.5 mhz adum5201 i iso(load) 105 ma c l =15pf, f = 12.5 mhz adum5202 i iso(load) 103 ma c l =15pf, f = 12.5 mhz i dd1 supply current, full v iso load 8 i dd1(max) 175 ma c l =0pf, f = 0 mhz, v dd = 3.3v, i iso =60ma input currents i ia , i ib ?10 +0.01 +10 a logic high input threshold v ih 0.7 v iso , 0.7 v idd1 v logic low input threshold v il 0.3 v iso , 0.3 v idd1 v logic high output voltages v oah , v obh v dd1 ? 0.2, v iso ? 0.2 5.0 v i ox = ?20 a, v ix = v ixh v oah , v obh v dd1 ? 0.5, v 1so ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.1 v i ox = 20 a, v ix = v ixl v oal , v obl 0.0 0.4 v i ox = 4 ma, v ix = v ixl ac specifications adum520xarwz minimum pulse width 9 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 10 1 mbps c l = 15 pf, cmos signal levels propagation delay 11 t phl , t plh 60 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 11 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 12 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 13 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum520xcrwz
adum5200/5201/5202 preliminary technical data rev. pra| page 6 of 23 parameter symbol min typ max unit test conditions minimum pulse width 13 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 14 25 mbps c l = 15 pf, cmos signal levels propagation delay 15 t phl , t plh 45 60 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 11 pwd 6 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/ c c l = 15 pf, cmos signal levels propagation delay skew 16 t psk 45 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 17 t pskcd 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 17 t pskcd 15 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output |cm h | 25 35 kv/s v ix = v dd or v iso , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output |cm l | 25 35 kv/s v ix = 0 v, v = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 all voltages are relative to their respective ground. 2 the contributions of supply current values for all four channels are combined at identical data rates. 3 v iso supply current available for external use when all data rates are below 2mbps. at data rates above 2mbps data i/o channels wi ll draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and be included in the v iso power budget. 4 the power demands of the quiescent operation of the data channels cannot be separated from the power supply section. efficien cy includes the quiescent power consumed by the i/o channels as part of its internal power consumption. 5 i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operat ing below 2mbps, requiring no additional dynamic supply curr ent. it reflects the minimu m current operating condition. 6 i dd1(d) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dynamic load conditions. resistive lo ads on the outputs should be treate d separately from the dynamic load. 7 this current is available for driving external loads at the v iso pin. all channels are simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dyn amic load conditions. refer to power consumption section for calculation of available current at l ess than maximum data rate. 8 i dd1(max) is the input current under full dynamic and v iso load conditions. 9 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 12 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 13 channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operat ed with identical loads.
preliminary technical data adum5200/5201/5202 rev. pra | page 7 of 23 electrical characteristics C 5v primary in put supply / 3.3v secondary isolated supply 1 4.5 v v dd1 5.5 v, v sel = gnd iso , all voltages are relative to their respective ground. all min/max specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t a = 25c, v dd = 5.0 v, v iso = 3.3 v, v sel = gnd iso . table 3. parameter symbol min typ max unit test conditions setpoint v iso 3.0 3.3 3.6 v i iso =0ma line regulation v iso(line) 1 mv/v i iso =50ma, v dd1 =4.5v to 5.5v load regulation v iso(load) 1 5 % i iso = 10ma to 100ma output ripple v iso(rip) 50 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 90ma output noise v iso(n) 130 mv p-p 20mhz bandwidth, c bo =0.1 f U 10 f, i iso = 90ma switching frequency f osc 180 mhz pwm frequency f pwm 625 khz dc to 2 mbps data rate 2 maximum output supply current 3 i iso(max) 100 ma f 1 mhz, v iso =3.0v efficiency at max. output supply current 4 30 % i iso = i iso(2,max) , f 1 mhz i dd1 supply current, no v iso load 5 i dd1(q) 9 13 ma i iso = 0ma, f 1 mhz 25 mbps data rate (crwz grade only) i dd1 supply current, no v iso load 6 adum5200 i dd1(d) 22 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5201 i dd1(d) 25 ma i iso = 0ma, c l =15pf, f = 12.5 mhz adum5202 i dd1(d) 27 ma i iso = 0ma, c l =15pf, f = 12.5 mhz available v iso supply current 7 adum5200 i iso(load) 96 ma c l =15pf, f = 12.5 mhz adum5201 i iso(load) 95 ma c l =15pf, f = 12.5 mhz adum5202 i iso(load) 93 ma c l =15pf, f = 12.5 mhz i dd1 supply current, full v iso load 8 i dd1(max) 230 ma c l =0pf, f = 0 mhz, v dd = 5v, i iso =100ma input currents i ia , i ib ?10 +0.01 +10 a logic high input threshold v ih 0.7 v iso v logic low input threshold v il 0.3 v iso v logic high output voltages v oah , v obh v dd1 ? 0.2, v iso ? 0.2 5.0 v i ox = ?20 a, v ix = v ixh v oah , v obh v dd1 ? 0.5, v 1so ? 0.5 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.1 v i ox = 20 a, v ix = v ixl v oal , v obl 0.0 0.4 v i ox = 4 ma, v ix = v ixl ac specifications adum520xarwz minimum pulse width 9 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 10 1 mbps c l = 15 pf, cmos signal levels propagation delay 11 t phl , t plh 60 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 11 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 12 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 13 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum520xcrwz minimum pulse width 13 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 14 25 mbps c l = 15 pf, cmos signal levels propagation delay 15 t phl , t plh 45 60 ns c l = 15 pf, cmos signal levels
adum5200/5201/5202 preliminary technical data rev. pra| page 8 of 23 parameter symbol min typ max unit test conditions pulse-width distortion, |t plh ? t phl | 11 pwd 6 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/ c c l = 15 pf, cmos signal levels propagation delay skew 16 t psk 45 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 17 t pskcd 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 17 t pskcd 15 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output |cm h | 25 35 kv/s v ix = v dd or v iso , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output |cm l | 25 35 kv/s v ix = 0 v, v = 1000 v, transient magnitude = 800 v refresh rate f r 1.0 mbps 1 all voltages are relative to their respective ground. 2 the contributions of supply current values for all four channels are combined at identical data rates. 3 v iso supply current available for external use when all data rates are below 2mbps. at data rates above 2mbps data i/o channels wi ll draw additional current proportional to the data rate. additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the power consumption section. the dynamic i/o channel load must be treated as an external load and be included in the v iso power budget. 4 the power demands of the quiescent operation of the data channels cannot be separated from the power supply section. efficien cy includes the quiescent power consumed by the i/o channels as part of its internal power consumption. 5 i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are operat ing below 2mbps, requiring no additional dynamic supply curr ent. it reflects the minimu m current operating condition. 6 i dd1(d) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dynamic load conditions. resistive lo ads on the outputs should be treate d separately from the dynamic load. 7 this current is available for driving external loads at the v iso pin. all channels are simultaneously driven at maximum data rate of 25mbps with full capacitive load representing the maximum dyn amic load conditions. refer to power consumption section for calculation of available current at l ess than maximum data rate. 8 i dd1(max) is the input current under full dynamic and v iso load conditions. 9 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 10 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 11 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 12 t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure, supply voltages, and output load within the recommended operating conditions. 13 channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operat ed with identical loads.
preliminary technical data adum5200/5201/5202 rev. pra | page 9 of 23 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ca 45 c/w thermocouple located at center of package underside, test conducted on 4 layer board with thin traces 3 . thermal shutdown thermal shutdown threshold thermal shutdown hysteresis ts sd ts sd-hys 150 20 c c t j rising 1 device considered a 2-terminal device; pins 1, 2, 3, 4, 5, 6, 7, and 8 shor ted together and pins 9, 10, 11, 12, 13, 14, 15, an d 16 shorted together. 2 input capacitance is from any input data pin to ground. 3 refer to the power considerations section for thermal model definitions table 5. ul (pending) csa (pending) vde (pending) recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 reinforced insulation, 2500 v rms isolation voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 300 v rms (424 v peak)maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul1577, each adum520x is proof tested by a pplying an insulation test voltage 3000 v rms for 1 sec (current leakage detection limit = 5 a). 2 in accordance with din v vde v 0884-10, each adum520x is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation volt age 2500 v rms 1 minute duration minimum external air gap (clearance) l(i01) >8 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) >8 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material gr oup (din vde 0110, 1/89, table 1)
adum5200/5201/5202 preliminary technical data rev. pra| page 10 of 23 din v vde v 0884-10 (vde v 0884-10) insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by protective circuits. the * marking on packages denotes din v vde v 0884-10 approval. table 7. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test vo ltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety-limiting values maximum value allowed in the event of a failure ( see figure 2) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 0 100 200 300 400 500 600 0 50 100 150 200 ambient tempearture (c) safe operating vdd1 current (ma) figure 2. thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747-5-2 recommended operating conditions table 8. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v dd @ v sel =0v v dd 3.0 5.5 v v dd @ v sel =5v v dd 4.5 5.5 v minimum load i iso(min) 10 ma 1 all voltages are relative to their respective ground.
preliminary technical data adum5200/5201/5202 rev. pra | page 11 of 23 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 9. parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature (t a ) ?40c to +105c supply voltages (v dd , v iso ) 1 ?0.5 v to +7.0 v input voltage (v ia , v ib , v e1 , v e2 ,rc sel , v sel ) 1, 2 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob ) 1, 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 (i o1 ) ?18 ma to +18 ma side 2(i oiso ) ?22 ma to +22 ma common-mode transients 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 3 see figure 2 for maximum rated current values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the absolu te maximum ratings may cause latch- up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 10. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 424 v peak 50-year minimum lifetime ac voltage, unipolar waveform basic insulation 600 v peak maximum approved working voltage per iec 60950-1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 dc voltage basic insulation 600 v peak maximum approved working voltage per iec 60950-1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 1 refers to continuous voltage magnitude imposed across the isolat ion barrier. see the insulation lifetime section for more detai ls. table 11. truth table (positive logic) rc in input rc sel output v sel input 1 v ddi input v iso output v ix input v ox output notes x h h 5.0v 5.0v x x master mode operation, self regulating x h l 5.0v 3.3v x x master mode operation, self regulating x h h 3.3v 5.0v x x master mode operation, self regulating x h l 3.3v 3.3v x x master mode operation, self regulating ext-pwm l x x x x x slave mode operation, regulation from another iso power part. l l l x 0v x x low power mode, converter disabled x x x x x h h data outputs valid fo r any active power configuration. x x x x x l l data outputs valid fo r any active power configuration h l x x x x x warning! this combination of rc in and rc sel is prohibited. damage will occur on the se condary due to exess output voltage at v iso . rcin must be either low or a pwm signal from a master iso power part..
preliminary technical data adum5200/5201/5202 rev. pra | page 12 of 23 pin configuration and fu nction descriptions figure 3. adum5200 pin configuration table 12. adum5200 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage 3.0v to 5.5 v. 2,8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 rc in regulation control input, in slave power configuration (rc sel =low), this pin is connected to the rc out of a master isopower device, or tied low to disable th e converter. in master/stand alone mode(rc sel =high) this pin has no function. this pin is weakly pulled to low. in noisy environments it should be tied to low or to a pwm control source. warning -this pin must not be tied high if rc sel is low, this combination will cause excessive volatge on the secondary, damaging the adum5000 and possibly devices that it powers. 6 rc sel control input, determines self regulation (ctl high) mode or slave mode(ctl low)allowing external regulation. this pin is weakly pulled to high. in noisy environments it should be tied either high or low. 7 nc no internal connection 9,15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v e2 data enable input, when high or nc the secondary outputs are active, when low the outputs are in a high z state.. 11 v sel output voltage selection: when v sel = v iso then the viso set point is 5.0v, when v sel = gnd iso then the viso setpoint is 3.3v. in slave regulation mode, this pin has no function. 12 nc no internal connection. 13 v ob logic output b. 14 v oa logic output a. 16 v iso secondary supply voltage output for seco ndary isolaton electronics and external loads, 3.3v (vsel low) or 5.0v (v sel high), 5.0v output functioanlity not guar anteed for a 3.3v primary supply input.
preliminary technical data adum5200/5201/5202 rev. pra | page 13 of 23 figure 4. adum5201 pin configuration table 13. adum5201 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage 3.0v to 5.5 v. 2,8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v ia logic input a. 4 v ob logic output b. 5 rc in regulation control input, in slave power configuration (rc sel =low), this pin is connected to the rc out of a master isopower device, or tied low to disable th e converter. in master/stand alone mode(rc sel =high) this pin has no function. this pin is weakly pulled to low. in noisy environments it should be tied to low or to a pwm control source. warning -this pin must not be tied high if rc sel is low, this combination will cause excessive volatge on the secondary, damaging the adum5000 and possibly devices that it powers. 6 rc sel control input, determines self regulation (ctl high) mode or slave mode(ctl low)allowing external regulation. this pin is weakly pulled to high. in noisy environments it should be tied either high or low. 7 v e1 data enable input, when high or nc the primary output is active, when lo w the outputs are in a high z state.. 9,15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 v e2 data enable input, when high or nc the secondary output is active, when lo w the outputs are in a high z state.. 11 v sel output voltage selection: when v sel = v iso then the viso set point is 5.0v, when v sel = gnd iso then the viso setpoint is 3.3v. in slave regulation mode, this pin has no function. 12 nc no internal connection. 13 v ib logic input b. 14 v oa logic output a. 16 v iso secondary supply voltage output for seco ndary isolaton electronics and external loads, 3.3v (vsel low) or 5.0v (v sel high), 5.0v output functioanlity not guar anteed for a 3.3v primary supply input.
adum5200/5201/5202 preliminary technical data rev. pra| page 14 of 23 figure 5. adum5202 pin configuration table 14. adum5202 pin function descriptions pin no. mnemonic description 1 v dd1 primary supply voltage 3.0v to 5.5 v. 2,8 gnd 1 ground 1. ground reference for isolator primary. pin 2 and pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 v oa logic output a. 4 v ob logic output b. 5 rc in regulation control input, in slave power configuration (rc sel =low), this pin is connected to the rc out of a master isopower device, or tied low to disable th e converter. in master/stand alone mode(rc sel =high) this pin has no function. this pin is weakly pulled to low. in noisy environments it should be tied to low or to a pwm control source. warning -this pin must not be tied high if rc sel is low, this combination will cause excessive volatge on the secondary, damaging the adum5000 and possibly devices that it powers. 6 rc sel control input, determines self regulation (ctl high) mode or slave mode(ctl low)allowing external regulation. this pin is weakly pulled to high. in noisy environments it should be tied either high or low. 7 v e1 data enable input, when high or nc the primary output is active, when lo w the outputs are in a high z state.. 9,15 gnd iso ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 nc no internal connection 11 v sel output voltage selection: when v sel = v iso then the viso set point is 5.0v, when v sel = gnd iso then the viso setpoint is 3.3v.. 12 nc no internal connection. 13 v ib logic input b. 14 v oa logic input a. 16 v iso secondary supply voltage output for seco ndary isolaton electronics and external loads, 3.3v (vsel low) or 5.0v (v sel high), 5.0v output functioanlity not guar anteed for a 3.3v primary supply input.
preliminary technical data adum5200/5201/5202 rev. pra | page 15 of 23 typical performance characteristics 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 0.02 0.04 0.06 0.08 0.1 0.12 output current (a) efficiency 3.3v in / 3.3v out 5v in / 3.3v out 5v in / 5v out figure 6. typical power supply efficiency at 5v/5v, 3.3v/3.3v and 5v/3.3v 0 0.02 0.04 0.06 0.08 0.1 0.12 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 input current (a) onput current (a) 3.3v in / 3.3v out 5v in / 3.3v out 5v in / 5v out figure 7. typical isolated output supply current, i iso as a function of external load, no dynamic current draw at 5v/5v, 3.3v/3.3v and 5v/3.3v 0 0.5 1 1.5 2 2.5 3 3.5 4 33.544.555.566.5 input voltage (v) input current (a) and power (w) idd po w e r figure 8. typical short circuit input current and power vs. v dd supply voltage figure 9. typical v iso transient load response 5v output 10%-90% load step figure 10. typical transient load response 3v output 10%-100% load step
adum5200/5201/5202 preliminary technical data rev. pra| page 16 of 23 figure 11. typical viso=5v output voltage ripple at 90% load figure 12. typical viso=3.3v output voltage ripple at 90% load 0 4 8 12 16 20 0 5 10 15 20 25 data rate (m bps) 5v in 5v out 3.3v in 3.3v out 5v in 3.3v out figure 13. . typical i ch supply current per forward data channel (15 pf output load 0.00 4.00 8.00 12.00 16.00 20.00 0 5 10 15 20 25 data rate (mbps) current (ma ) 5v in 5v out 3.3v in 3.3v out 5v in 3.3v out figure 14 typical i ch supply current per reverse data channel (15 pf output load 0.00 1.00 2.00 3.00 4.00 5.00 0 5 10 15 20 25 dat a rat e ( m b p s ) current (ma ) 5v 3.3v figure 15. typical i iso(d) dynamic supply current per input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 0 5 10 15 20 25 data rate (mbps) current (ma ) 5v 3.3v figure 16. typical i iso(d) dynamic supply current per output (15pf output load)
adum5200/5201/5202 rev. pra | page 17 of 23 terminology i dd1(q) i dd1(q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the i/o pins are oper- ating below 2 mbps, requiring no additional dynamic supply current. i ddio(q) reflects the minimum current operating condition. i dd1(d) i dd1(d) is the typical input supply current with all channels simultaneously driven at maximum data rate of 25 mbps with full capacitive load representing the maximum dynamic load conditions. resistive loads on the outputs should be treated separately from the dynamic load. i dd1(max) i dd1(max) is the input current under full dynamic and v iso load conditions. t phl propagation delay t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. propagation delay skew (t psk ) t psk is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel-to-channel matching channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
adum5200/5201/5202 preliminary technical data rev. pra | page 18 of 23 application information theory of operation the dc/dc converter section of the adum520x works on principles that are common to most modern power supply designs. it is implemented as a secondary side controller with isolated pwm feedback. v dd1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. power is transferred to the secondary side where it is rectified to a dc voltage. the power is then regulated to either 3.3or 5v and supplied to the secondary side data section and to the v iso pin for external use. active feedback is implemented by a digital feedback path. the output regulator creates a pulse width modulated signal which is coupled to the input side and switches the oscillator on and off regulating the power. feedback allows for significantly higher power, efficiency, and synchronization of multiple supplies. the adum520x provides its regulation control output (rcout) signal that can be connected to other isopower devices. this allows a single regulator to control multiple power modules without contention. when auxiliary power modules are present, the v sio pins can be connected together to work as a single supply. since there is only one feedback control path, the supplies will work together seamlessly. the adum520x can only be a source of regulation control, other devices there is hysteresis into the input v dd input voltage detect circuit. once the dc/dc converter is active, the input voltage must be decreased below the turn on threshold to disable the converter. this feature ensures that the converter does not go into oscillation due to noisy input power. pc board layout the adum520x digital isolator with a ? w iso power integrated dc/dc converter requires no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (figure 17). the power supply section of the adum520x uses a very high oscillator frequency to efficiently pass power through its chip scale transformers. in addition, the normal operation of the data section of the i coupler introduces switching transients on the power supply pins. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance high frequency capacitor, ripple suppression and proper regulation require a large value capacitor. these are most conveniently connected between pins 1 and 2 for v dd1 and between pins 15 and 16 for v iso . to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0. 1 f, and 6.6 f. it is strongly recommended that a very low inductance ceramic or equivalent capacitor be used for the smaller value. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 4 mm. installing the bypass capacitor with traces more than 4 mm in length may result in data corruption. a bypass between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless both common ground pins are connected together close to the package. figure 17. recommended printed circuit board layout in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins exceeding the devices absolute maximum ratings, specified in table 9 thereby leading to latch-up and/or permanent damage. the adum520x is a power device that dissipates about 1w of power when fully loaded and running at maximum speed. since it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the pcb through the gnd pins. if the device will be used at high ambient temperatures, care should be taken to provide a thermal path from the gnd pins to the pcb ground plane. the board layout in figure 17 shows enlarged pads for pins 2, 8, 9, and 15. multiple vias should be implemented from the pad to the ground plane. this will significantly reduce the temperatures inside of the chip. the dimensions of the expanded pads are left to discretion of the designer and the available board space. thermal analysis the adum520x parts consist of four internal die, attached to a split lead frame with two die attach paddles. for the purposes of thermal analysis it is treated as a thermal unit with the highest junction temperature reflected in the ja from table 4. the value of ja is based on measurements taken with the part mounted on a jedec standard 4 layer board with fine width traces and still air. under normal operating conditions the adum520x will operate at full load across the full temperature range without derating the output current. however, following the recommendations in the pc board layout section will
adum5200/5201/5202 rev. pra | page 19 of 23 decrease the thermal resistance to the pcb allowing increased thermal margin it high ambient temperatures. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output may differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 03786-018 figure 18. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum520x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum520x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see error! reference source not found. ) by the watchdog timer circuit. the limitation on the adum520xs magnetic field immunity is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adum520x is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( d /dt ) = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum520x and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 19. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 03786-019 figure 19. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum520x transformers. figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum520x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, one would have to place a 0.5 ka current 5 mm away from the adum520x to affect the components operation.
adum5200/5201/5202 preliminary technical data rev. pra | page 20 of 23 magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 03786-020 figure 20. maximum allowable current for various current-to-adum520x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the v dd1 power supply input provides power to the i coupler data channels as well as the power converter. for this reason, the quiescent currents drawn by the data converter and the primary and secondary i/o channels cannot be determined separately. all of these quiescent power demands have been combined into the i dd1(q) current as shown in figure 21. the total i dd1 supply current will be the sum of the quiescent operating current, dynamic current i dd1(d) demanded by the i/o channels, and any external i iso load. figure 21 power consumption within the adum520x both dynamic i/o current is consumed only when operating at channel at speeds higher than the rate f r . since each channel will have a dynamic current that is determined by its data rate, figure 15 shows the current for a channel in the forward direction, which means that the input on the primary side of the part. figure 16 shows the current for a channel in the reverse direction, which means that the input on the secondary side of the part. both figures assume a typical 15pf load. the following relationship allows the total i dd1 current to be calculated. i dd1 = (i iso v iso )/(e v dd1 ) + i chn ; n = 1to 4 equation 1 where : i dd1 is the total supply input current. i chn is the current drawn by a single channel determined from figure 15 or figure 16 depending on channel direction. i iso is the current drawn by the secondary side external loads. e is the power supply efficiency at 100ma load from figure 6 at the v iso and v dd1 condition of interest. the maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. i iso(load) = i iso(max) - i iso(d)n ; n = 1to 4 equation 2 where: i iso(load) is the current available to supply an external secondary side load. i iso(max) is the maximum external secondary side load current available at v iso . i iso(d)n is the dynamic load current drawn from v iso by an input or output channel, as shown in figure 15 and figure 16. data is presented assuming a typical 15pf load the preceding analysis assumes a 15pf capacitive load on each data output. if a capacitive load larger than 15pf, he additional current must be included in the analysis of i dd1 and i iso(load) . to deter m ine i dd1 in equation 1, additional primary side dynamic output current i aod is added directly to i dd1 . additional secondary side dynamic output current i aod is added to i iso on a per channel basis. to deter m ine i iso(load) in equation 2, additional secondary side output current i aod is subtracted from i iso(max) on a per channel basis. for each output channel with c l greater than 15pf, the additional capacitive supply current is given by: i aod = 0.5 10 ?3 (c l -15) v iso ) (2f ? f r ) f > 0.5 f r equation 3 where: c l is the output load capacitance. (pf). v iso is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input channel refresh rate (mbps).
adum5200/5201/5202 rev. pra | page 21 of 23 power considerations the adum520x converter primary side, data input channels on the primary side and data input channels on the secondary side are all protected from premature operation by under voltage lock out (uvlo) circuitry. below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. outputs are held in their default low state. this is to prevent transmission of undefined states during power up and power down operations. during application of power to v dd1 , the primary side circuitry is held idle until the uvlo preset voltage is reached. at that time the data channels initialize to their default low output state until they receive data pulses from the secondary side. the primary side input channels sample the input and send pulse to the inactive secondary output. the secondary side converter begins to accept power from the primary and the v iso voltage starts to rise. when the secondary side uvlo is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a dc refresh pulse, is received from the corresponding primary side input. it could take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. secondary side inputs sample their state and transmit it to the primary side. outputs are valid one propagation delay after the secondary side becomes active. because the rate of charge of the secondary side is dependant on loading conditions, input voltage and output voltage level selected, care should be taken in the design to allow the converter to stabilize before valid data is required. when power is removed from v dd1 , the primary side converter and coupler shut down when uvlo is reached. the secondary side stops receiving power and starts to discharge. the outputs on the secondary side will hold the last state that they received from the primary until either the uvlo level is reached and the outputs are put in their default low state or the output detects a lack of activity from the input and the outputs are set to default before secondary power reaches uvlo. increasing available power the adum5200 devices are designed with capability of running in combination with other compatible iso power devices. the rc in and rc sel pins allow the adum5200 to receive a pwm signal from another device through the rc in pin and act as a slave to that control signal. the rc sel pin chooses whether the part will act as a stand alone self regulated device or slave device. when the adum5200 is acting as a slave, its power is regulated by the master device allowing multiple isopower parts to be combined in parallel while sharing the load equally. when the adum5000 is configured as a stand alone unit, it generates its own pwm feedback signal to regulate itself and slave devices. the adum5000 can act as a master or a slave deice, the adum5400 can only be a master/stand alone device, and the adum5200 can only be a slave/stand alone device. this means that the adum5000, adum5200, and adum5400 can only be used in certain master slave combinations as listed in table 15. slave adum5000 adum5200 adum5400 adum5000 y y n adum5200 n n n master adum5400 y y n table 15 allowed combinations of isopower parts the allowed combinations of master and slave configured parts listed in table 15 is sufficient to make any combination of power and channel count. table 16 illustrates how isopower devices can provide many combinations of data channel count and multiples of the single unit power. number of data channels 0 2 4 6 adum5000 master adum520x master adum540x master adum540x master adum12xx 1 unit power adum5000 master adum500x master adum540x master adum540x master adum5000 slave adum5200 slave adum5200 slave adum520x slave 2 unit power adum5000 master adum5000 master adum540x master adum540x master adum5000 slave adum5000 slave adum5000 slave adum520x slave 3 unit power adum5000 slave adum520x slave adum5000 slave adum5000 slave table 16 configurations for power and data channels insulation lifetime all insulation structures will eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependant on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum520x. adi performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors
adum5200/5201/5202 preliminary technical data rev. pra | page 22 of 23 for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum520x depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 22, figure 23, and figure 24 illustrate these different isolation voltage waveforms. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the ac bipolar condition determines adis recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 year service life. the working voltages listed in table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross insulation voltage waveform that does not conform to figure 23 1 or figure 24 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50 year lifetime voltage value listed in table 10. 0v rated peak voltage 05007-021 figure 22. bipolar ac waveform 0v rated peak voltage 05007-022 figure 23. unipolar ac waveform 0v rated peak voltage 05007-023 figure 24. dc waveform 1 the voltage presented in figure 23 is shown as sinusoidal for illustration purposes only. it is meant to repr esent any voltage waveform varying between 0 and some limiting value. th e limiting value can be positive or negative, but the voltage cannot cross 0v.
adum5200/5201/5202 rev. pra | page 23 of 23 pr07540-0-5/08(pra) outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) coplanarity 0.10 figure 25. 16-lead standard small outline package [soic_w] wide body (rw-16) dimension shown in millimeters and (inches) ordering guide model number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range (c) package option adum5200arwz 1,2 2 0 1 100 40 ?40 to +105 16-lead soic_w adum5200crwz 1,2 2 0 25 70 3 ?40 to +105 16-lead soic_w adum5201arwz 1,2 1 1 1 100 40 ?40 to +105 16-lead soic_w adum5201crwz 1,2 1 1 25 70 3 ?40 to +105 16-lead soic_w adum5202arwz 1,2 0 2 1 100 40 ?40 to +105 16-lead soic_w adum5202crwz 1,2 0 2 25 70 3 ?40 to +105 16-lead soic_w 1 tape and reel are available. the a dditional -rl7 suffi ce designates a 7 (1,000 un its) tape and reel options. 2 z = pb-free part.

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